MIPS‑board with DSP accelerator
MIPS-board with DSP accelerator is intended for real-time digital signal processing (a digital filtering, Fourier analysis, signal compression and coding), output of results on colour or B/W graphic LCD display (TFT/STN 800x600) and high-speed information interchange (10/100 Ethernet, USB) with external devices.
The board possesses the advanced periphery (PCMCIA, UART, I2S, AC ’ 97, SD/MMC, IrDA) and is positioned as alternative on speed, service functions, power consumption and cost to devices on micro-PC base and to mixed circuits DSP+FPGA.
· SSI0 and SSI1 controller (two synchronous sequential duplexes);
· Secure Digital SD0 and SD1 (two Flash SD/MMC cards);
· LCD TFT/STN controller 800x600;
· PCMCIA controller (translate through FPGA);
· SDRAM controller. It is set from 32 MB up to 256 MB;
· SRAM/Flash controller. It is set from 8 MB up to 128 MB;
· two completely separate to addresses, the data and control signals buses for SDRAM and SRAM;
· two DMA channels from FPGA Virtex‑II;
· FPGA Virtex‑II has 38-48-68 LVDS I/O lines for 256 thousand 500 thousand 1million gates capacity;
· FPGA Virtex‑II in capacity 256 thousand and 500 thousand gates has 2 external independent bank SRAM 256Ê x 16, at capacity 1 million gates - 4 external independent bank SRAM 256Ê x 16;
· two LED indicators of modes.
· 32-bits MIPS core 300, 400 or 500MHz;
· 10/100 Ethernet MAC;
· USB Device and Host controller;
· UART0, UART1, UART3;
· IrDA controller;
· AC’97 controller;
· I2S controller;
· full-scale support of OS Linux, Windows CE, VxWorks. The presence of the big number of ready libraries and drivers of I/O devices, information storage and view, fonts, etc.;
· the optimum price/productivity relationship is provided with hardware scalability of the board - a wide range of memory volumes (8MB … 256MB), CPU speed (266MHz…500MHz) and FPGA capacity (from 256 thousand up to 1 million gates);
· FPGA Virtex-II (from 256 thousand up to 1 million gates) and availability up to 4 independent banks SRAM 256Kx16 allows to organize real-time preprocessing of dataflow (a digital filtering, Fourier transformation, etc.) on frequencies up to 120MHz … 180ÌHz;
· hardware support of video, network and system interfaces by peripherals controllers integrated in CPU.
Embedded software of a board include:
· monitor YAMON (standard MIPS monitor):
o provides command line interface through RS-232;
o provides connection with the central computer through Ethernet (TFTP);
o supports work with FLASH, including operations of erasing, record and verification of any sections, including YAMON part;
o operates a configuration of OS start process, including automatic,
· Linux 2.4.20 kernel with support of all processor hardware interfaces (Ethernet, USB, UART, IrDA, PCMCIA, LCD, etc.);
· the file system JFFS2 operating in Flash. Includes:
î driver for work with Xilinx for Linux;
o set of standart Linux utilities for supply of full functionality from a command line;
o graphic QT3 libraries for a usual mode and with multithreading support, including language support by means of UNICODE.
Structure of the board
The processor module is executed on 8-layer MPCB with the dimensions 100mm x 76mm. It has two 100-pins communication slots: integrated peripherals and user. All signals of internal peripherals controllers (except for PCMCA and external LCD controller 1600x1200 points - S1D13505, Epson; MB8629x, Fujitsu) are outputed from the processor on the first (peripheral) slot. PCMCA interface and management of external LCD contollers are translated through FPGA. For user it is available up to 68 lines outputed on the second (user) slot which if necessary can be configured as LVDS outputs.
The main advantages of use of the AMD Alchemyä in comparison with existing solutions on the basis of ARM architecture(Intel, Samsung, Cyrrus Logic), SHx (Toshiba), PowerPC (Motorola, AMCC) is:
· two completely separate buses to addresses, the data and control signals for dynamic and static memory. The operating system (Linux, VxWorks or Windows CE) and external high-speed data streams function independently from each other. Throughput of both buses (100MHz) is completely used unnecessary to divide their potential between system and embedded tasks;
· the separate topology of high-speed lines of the board with the minimal number of connected chips allows to receive conductors of the least length with the simplified requirements to their impedances;
· support of peripherals by the controllers integrated in CPU does not demand almost any tie except for protection against an overvoltage. All available CPU interfaces are outputed on the external peripherals slot;
· four independent banks of fast static memory (10 ns, 256 kB, 16 bis) provide a page input/output and preprocessing of two information streams. All banks have own buses of the address/data/control.
The board has DC-DC converters from a power +9V … +24V. For increase of functionality the power supply system is distributed on both modules included in a board. Interface module provides:
· +3.3V - basic digital supply;
· +5V - USB and DC‑DC supply with galvanic separation for RS‑232;
· +12V - supply of LCD panel backlights inverter.
The processor module has two own DC-DC converters:
· +1.2V - voltage of CPU core supply;
· +1.5V - voltage of FPGA core supply.
If necessary own DC-DC converters of the processor module can be switched - off, and supply is sent through the user slot from the interface module.
Power consumption of the processor module depending on CPU speed and SDRAM makes from 1,6 W up to 3,5 W.
Cost of the componentry of an individual unit does not exceed a mark 185$ in the minimal configuration – CPU 330MHz, Flash 8MB, SDRAM 16MB, FPGA Virtex II 250 thousand gates, 2 SRAM banks 256kBx16. At the use of external power supplies +1.2V and +1.5V the price of componentry can be reduced up to 165$.